1. Field of the Invention
The present invention generally relates to multilayer semiconductor devices, and more particularly to improvements in gate turn off (GTO) thyristor structures to produce a solid state switch having improved characteristics.
2. Description of the Prior Art
FIG. 1 shows a conventional thyristor capable of blocking forward and reverse voltage. These devices have a continuous P layer over the entire anode area. Conventional shorted emitter thyristors capable of blocking only forward voltage have P islands at the anode end. In this case, the anode metal disc shorts the P islands to the adjacent N region at the anode surface as illustrated in FIG. 2. Such a device is asymmetrical, i.e., it cannot block reverse voltage. In both devices the cathode has emitter shorts as shown in FIG. 1. The metal contact to the N emitter region at the cathode end partially overlaps the P base material. The metal contact to the P region is the gate lead, while the cathode is the metal contact to the N region. The purpose of the shorts is to shunt displacement current that would otherwise traverse a vertical path through all junctions and act as a turn on gate pulse. Thus, by offering an easier path around the emitter junctions, undesired internal transistor action is prevented when the device is in its blocking state and a transient change in blocking voltage occurs due to external causes.
FIG. 2 shows a recent improvement wherein an N+ layer is diffused into the N- anode before diffusing in the P+ islands. This N+ layer allows the wafer to be thinner since, in the off state, it stops the depletion layer from spreading further toward the anode. The thinner wafer has a lower on state voltage drop and hence higher efficiency.
Another recent improvement is to create a fast recovery diode at the outer region of the wafer using the P base (gate) diffusion and the N- and N+ regions described. This requires an isolating groove to prevent carriers associated with diode current from diffusing into the four layer device region which would cause the device to turn on when forward blocking voltage is reapplied. FIG. 2 illustrates this structure. Such a fast diode inversely connected across the device is needed in most inverter circuits.
GTO thyristors are similar to conventional shorted emitter thyristors as illustrated in FIG. 2. Current is put into the P base via the gate and holes flow from the gate to the N cathode. This causes electrons to flow from the N emitters into the base. Some of these electrons, in fact more than half of them, diffuse into the N- layer above the base. This causes electrons to flow in the anode side N+ region, creating an IR drop adjacent to the P islands. Holes are then emitted by the anode P regions into the N- region and travel toward the cathode. These holes are minority carriers when they are in the N- region. Similarly, electrons emitted by the N cathode emitter into the P base are minority carriers in the P region.
When the holes emitted by the anode P region at J1 shown in FIG. 2 reach the P base region at J2 and subsequently enter the N emitter region at J3, they are equivalent to hole current created by gate input current. Consequently, gate input current is no longer required, and the device is said to be latched on. The equivalent circuit of a conventional shorted emitter GTO is shown in FIG. 3.
Some of the minority carriers recombine with majority carriers enroute. The fraction of the holes emitted by P1+ that reach P2 is called .alpha..sub.1. The fraction of the electrons emitted by N2 that reach N1- is .alpha..sub.2. When an electron reaches the N side of J2, a different electron immediately moves into the anode P region as a minority carrier. Together, .alpha..sub.1 and .alpha..sub.2 determine the behavior of the device. The anode current is given by the following equation: ##EQU1## where I.sub.g is the gate current, I.sub.d is the thermally generated diffusion current, and I.sub.sc is the space charge current generated in the depletion region of J1. I.sub.d and I.sub.sc can be neglected.
In conventional devices, .alpha..sub.1 and .alpha..sub.2 increase with current. .alpha..sub.1 is usually 0.1 to 0.3 since the anode emitted holes must travel a long distance through N1 to reach P2 and many recombine with electrons. .alpha..sub.2 is 0.7 to 0.9 since P2 is relatively thin. If current increases enough so that the sum of .alpha..sub.1 and .alpha..sub.2 reaches 1, I.sub.A is limited only by external components, and the device is said to be on. Such a conventional device can be turned off by applying a negative gate voltage. This causes the gate to intercept holes emitted by the anode P material that otherwise would reach the N2 emitter regions. Electrons are then no longer emitted by the N2 emitter regions, and the device turns off.
The turn off of conventional GTO devices is made more difficult with clamped inductive loads as illustratively shown in FIG. 4. The problem here is that current is forced to continue unabated until the voltage across the device rises to the clamp voltage level, typically 1000 V. Furthermore, for the gate to intercept all holes emitted by the anode P material, the gate must have good access to all the P2 material at the junction J3 of P2 and N2. This requires very small N2 islands and a fine mesh for the gate metallization. Photolithographic methods are required, as with the manufacture of integrated circuits.
It is also desirable to use a low reverse gate voltage during turn off to avoid breaking down the low voltage P2N2 junction. Hence, a reverse gate voltage of no more than a few volts is preferred. For this low voltage to create a sufficient gradient to prevent holes from reaching N2 requires dimensions in the range of 10 to 100 microns for the N2 islands. To accomplish turn off, &lt;100&gt; crystal silicon has been etched with V-grooves to create N emitter islands of small dimensions which are vertically above the P base and can be cut off by a reverse gate voltage. &lt;111&gt; crystal silicon is standard in other applications, however, and is less costly and carriers have better mobility than in &lt;100&gt; crystal silicon. A V-groove etched &lt;100&gt; crystal silicon device is illustrated in FIG. 5. As may be appreciated from this illustration, the gate contact is difficult to make on the etched surface and the emitter land size possible is not as small as may be preferred.
The foregoing and other prior art are disclosed in the following U.S. Pat. Nos.: 3,972,014; 3,979,766; 3,996,601; 4,011,579; 4,032,958; 4,054,893; 4,163,241; 4,190,853; 4,214,255; 4,278,476; 4,286,279 and 4,291,325.